Gnu Instruction Scheduler: Ailments and Cures in Context of Superscalarity

| In the past, the GNU C compiler (GCC) has been successfully ported to several superscalar microprocessors. For that purpose, the instruction timing of the target processor usually had been modeled in a straightforward manner. Unfortunately, in our experience, this is likely to lead astray the instruction scheduler. In this paper we describe some of our experiments that revealed such aws, concerning the DEC Alpha 21064 as well as other super-scalar RISC processors. We analyze the circumstances that led to poorly scheduled code, and demonstrate how the machine description supplied for a superscalar processor can be modiied to x some of these problems without hampering the portability of the GCC. On the other hand we show situations for which we do not have a solution within the given framework.